1. Field of the Invention
The present invention relates generally to a method for fabricating semiconductor devices and, more particularly, to a method for forming ultra-shallow junctions using laser annealing with an amorphous carbon layer as an energy absorber layer.
2. Description of the Background Art
As a design rule for high performance semiconductor device is reduced, recent research and development efforts are focused on formation of ultra-shallow junction. Therefore, research and development are being in progress.
For example, in semiconductor devices having a gate length of less than 250 nm, that is, in MIS (Metal-Insulator-Semiconductor) transistors, source/drain extension (hereinafter, referred to as SDE) doping layers having ultra-shallow junctions are formed on inner sides of source/drain regions. In a conventional method, this SDE layer is formed by implanting impurity ions and performing a rapid thermal process (hereinafter referred to as RTP) and thereby, activating dopants in the SDE doping layer and source/drain regions
The above-described method is advantageous in forming a transistor having gate lengths of more than 130 nm. However, it has several drawbacks when applied to high performance transistors having gate lengths of less than 100 nm.
First, when the high performance transistor is formed, it is required to maintain a junction depth of the SDE doping layer less than 35 nm. However, when junction depth of the SDE doping layer is less than 35 nm, a desired doping degree of the SDE doping layer is not maintained due to the solid solubility limit, thereby causing abrupt increase of sheet resistance. As a result, it is difficult to obtain a high performance transistor.
Therefore, laser thermal processes have been developed to solve the above problems.
FIG. 1 is a graph plotting sheet resistance versus junction depth in each method for forming ultra-shallow junctions, where reference code A indicates sheet resistance according to junction depths in which RTP is performed to activate doped impurities and reference code B indicates those in which laser annealing is performed. Reference code C indicates scaling rule requirements of junction depth and sheet resistance.
As shown in FIG. 1, when RTP is performed to activate impurities (A), scaling rule requirements of junction depth and sheet resistance are not fulfilled. However, when laser annealing is performed (B), they are fulfilled.
A fabrication method for making 70 nm MOSFET using laser annealing, as proposed by Bin Yu et al., will be described with reference to FIGS. 2A to 2C. (IEDM 1999, xe2x80x9c70 nm MOSFET with Ultra-Shallow, Abrupt, and Super-Doped S/D Extension Implemented by Laser Thermal Processxe2x80x9d).
Referring to FIG. 2A, a gate 23 having a gate oxide film 22 is formed on an active region of silicon substrate 20 defined by a trench type isolation layer 21 through well-known processes. Then, a first spacer 24, made of silicon nitride layer (Si3N4), is formed on the sidewalls of the gate 23. An ion implantation process and a rapid thermal process are sequentially performed to form source/drain regions 25a and 25b on the silicon substrate 20 at both sides of gate 23, including the first spacer 24.
Referring to FIG. 2B, the first spacer 24 is removed and ions are implanted on the resulting structure to form a SDE doping layer. Then, laser annealing is performed to selectively melt and solidify the amorphous surfaces of source/drain regions 25a and 25b, thereby forming a SDE doping layer 26, activated in high concentration on silicon substrate 20 at both sides of gate 23.
Referring to FIG. 2C, a second spacer 27 is formed on sidewalls of gate 23 by oxide film deposition and blanket etching and then a metal layer, for example, a cobalt layer is deposited to a predetermined thickness on the resulting structure. Then, annealing is performed so that cobalt of the cobalt layer may respond to substrate silicon, thereby forming a cobalt silicide layer 28 on the surface of source/drain regions 25a and 25b and on the upper surface of the gate 23.
Ken-ichi Goto proposed a method that the activated dopant concentration of a contact formation region can be maintained at greater than 1021/cm3 by using laser annealing after implanting the source/drain ions to improve contact resistance. The ultra-low resistance contact formation method by laser annealing will be described with reference to FIGS. 3A to 3C. (IEDM 1999, xe2x80x9cUltra-Low Contact Resistance for Deca-nm MOSFETs by Laser Annealingxe2x80x9d).
Referring to FIG. 3A, a gate 33 having a gate oxide film 32 is formed on an active region of silicon substrate 30 defined by isolation layer 31. And, ions are implanted to form source/drain extension doping layer and rapid thermal treatment is performed thereby, forming a SDE doping layer 34 electrically activated on the surface of substrate 30 at both sides of the gate 33.
Referring to FIG. 3B, a spacer 35 is formed on sidewalls of gate 33 and ions are implanted, thereby forming inactivated doping layer 36 to form source/drain regions on a silicon substrate 30 at both sides of gate including the spacer 35.
Referring to FIG. 3C, in order to obtain ultra-low resistance contact, source/drain regions 36a and 36b are formed using laser annealing and, at the same time, the surface of the source/drain regions 36a and 36b and the upper surface of gate 33 are transformed into an activated doping layer 37 in a high concentration.
Thereafter, a rapid thermal treatment at a low temperature of 800xc2x0 C. and interconnection process are performed to complete the formation of the transistor.
The above-mentioned method using laser annealing is advantageous to fabrication of a transistor having a silicon gate. However, as shown in FIG. 4, it is difficult to apply to fabrication of a transistor having a metal gate 42d on the upper part of a gate 42, since the metal gate 42d is transformed during laser annealing due to the fact that the metal gate 42d has high laser absorption rate. In FIG. 4, reference numeral 40 indicates a silicon substrate, reference numeral 41 is a isolation layer, reference numeral 42a is a gate insulating layer, reference numeral 42b is a silicon gate, reference numeral 42c is a diffusion preventing layer, reference numeral 43a is a source region, reference numeral 43b is a drain region and reference numeral 44 is a SDE doping layer.
In order to solve the above-described problems, a method has been developed that includes a step prior to laser annealing, in that a metal laser absorber layer, for example, a refractory metal thin film such as a Ti/TiN layer, is deposited on the surface of the substrate, thereby preventing an excessive rise in temperature of the metal gate. However, problems exist in that the melting point of Ti is 1,667xc2x0 C., very similar to that of Si, 1,412xc2x0 C. Therefore, the Ti components remain in the oxide film after the Ti/TiN layer is removed.
Therefore, an object of the present invention is to provide a method for forming an ultra-shallow junction capable of preventing transformation of a metal gate using laser annealing.
Another object of the present invention is to provide a method for forming an ultra-shallow junction using laser annealing to be applied to fabrication of a high performance device without transformation of the gate.
In order to achieve the above-described objects, an embodiment of the present invention comprises the steps of: preparing a silicon substrate having isolation layers thereon; forming a gate which has a stacked structure of a gate insulating layer, a polysilicon layer and a metal layer on the silicon substrate; forming a sacrificial spacer on sidewalls of the gate; forming source/drain regions on the silicon substrate region at both sides of the gate including over the sacrificial spacer; removing the sacrificial spacer; doping impurities to form a source/drain extension doping layer on the silicon substrate at both sides of the gate; depositing a reaction preventing layer and an amorphous carbon layer as a laser absorber layer on the resulting structure; forming source/drain extension doping layers on inner sides of the source/drain regions by laser annealing; and removing the amorphous carbon layer.
Another embodiment of the present invention comprises the steps of: preparing a silicon substrate having trench type isolation layers to define an active region; forming a gate having a stacked structure of a gate insulating layer, a polysilicon layer, a diffusion preventing layer, a metal layer and a hard mask layer on an active region of the silicon substrate; forming a thin oxide layer on the surface of the silicon substrate and the side of the polysilicon layer by performing oxidation processes; depositing a thin silicon nitride layer as an etching preventing layer on the resulting structure; forming a sacrificial spacer on the sidewalls of the gate on which the silicon nitride layer is deposited; forming source/drain regions on the silicon substrate region at both sides of gate including the sacrificial spacer; removing the sacrificial spacer, the silicon nitride layer and the oxide layer formed on the surface of the silicon substrate; doping impurities in low energy to form source/drain extension doping layers on the silicon substrate at both sides of the gate; depositing a silicon oxide layer as a reaction preventing layer and an amorphous carbon layer as a laser absorber layer on the resulting structure; forming source/drain extension doping layers on inner sides of the source and drain regions by performing laser annealing; and removing the amorphous carbon layer using an O2 plasma etching process.
Still another embodiment of the present invention comprises the steps of: preparing a silicon substrate having isolation layers thereon; forming a gate having a stacked structure of a gate insulating layer, a polysilicon layer and a metal layer on the silicon substrate; forming source/drain extension doping layers on silicon substrates at both sides of the gate; forming a spacer on the sidewalls of the gate; doping impurities on the silicon substrate at both sides of the gate including the spacer to form source/drain regions; depositing a reaction preventing layer and an amorphous carbon layer as an energy absorber layer on the resulting structure; forming source and drain regions on the silicon substrate regions at both sides of gate including the spacer by using laser annealing; and removing the amorphous carbon layer.
Still another embodiment of the present invention comprises the steps of: preparing a silicon substrate having trench type isolation layers thereon to define an active region; forming a gate having a stacked structure of a gate insulating layer, a polysilicon layer, a diffusion preventing layer, a metal layer and a hard mask layer; forming source/drain extension doping layers by doping impurities and rapid thermal treatment on the silicon substrate region at both sides of the gate; depositing a thin silicon nitride layer as an etching preventing layer on the resulting structure; forming a spacer on sidewalls of the gate having the silicon nitride layer thereon; doping impurities to form source and drain regions on the silicon substrate at both sides of gate including the spacer; depositing a silicon oxide layer as a reaction preventing layer and an amorphous carbon layer as an energy absorber layer on the resulting structure; forming source and drain regions on the silicon substrate at both sides of the gate including the spacer using laser annealing; and removing the amorphous carbon layer by using an O2 plasma etching process.
The objects and features of the invention may be understood with reference to the following detailed description of several illustrative embodiments of the invention, taken together with the illustrations in the accompanying drawings.